Hi,
This is Kavini From Agile Enterprise Solutions,
This is in reference to the following position.
***** Please reply with Resume, Work Authorization , Rate & Contact Details ASAP ****
Passport no. is mandatory for H1B's
Job Title: Physical Design
Location:Dallas, TX
Duration: contract
Key Skills:
Audit customer design for PnR processing
Perform physical design flow from Netlist to GDSII with timing closure, DRC clean: Audit Netist/ timing constraints; Clock tree synthesis and Hold fixing; Routing and post routing optimization
Timing sign-off: Timing clean database with timing signoff tools
Synthesis & Floor planning, Power structure designing
Work on complex block place & route and/or top level place and route (P&R) for advanced nodes (40nm and below)
Interface with Front End, DFT team, Physical Verification team
Assist in interfacing with IP vendors and EDA vendor
Analyze and propose solution to meet timing closure and schedule
Assist in communicating with customer and manage expectations
Background and Experience Requirements:
To be qualified for this PD Engineer position candidates must possess
7+ years as a ASIC P&R engineer experience with Atoptech, Synopsys and Cadence: P&R, PT STA, Formal verification experience with SDC constraints debug complex high speed interfaces (serdes, DDR3, MIPI)
experience with IP integration
TCL and scripting
experience with advanced nodes (40nm and below)
BS of Electrical Engineering or similar. MSEE a plus.
Outstanding communications skills (including English) and team player
Thanks & Regards
Kavini Bitla
Agile Enterprise Solutions, Inc
Email : kavini_bitla@aesinc.us.com || www.aesinc.us.com
Agile Enterprise Solutions Inc || "Ensuring Client's Success"||
-- This is Kavini From Agile Enterprise Solutions,
This is in reference to the following position.
***** Please reply with Resume, Work Authorization , Rate & Contact Details ASAP ****
Passport no. is mandatory for H1B's
Job Title: Physical Design
Location:Dallas, TX
Duration: contract
Key Skills:
Audit customer design for PnR processing
Perform physical design flow from Netlist to GDSII with timing closure, DRC clean: Audit Netist/ timing constraints; Clock tree synthesis and Hold fixing; Routing and post routing optimization
Timing sign-off: Timing clean database with timing signoff tools
Synthesis & Floor planning, Power structure designing
Work on complex block place & route and/or top level place and route (P&R) for advanced nodes (40nm and below)
Interface with Front End, DFT team, Physical Verification team
Assist in interfacing with IP vendors and EDA vendor
Analyze and propose solution to meet timing closure and schedule
Assist in communicating with customer and manage expectations
Background and Experience Requirements:
To be qualified for this PD Engineer position candidates must possess
7+ years as a ASIC P&R engineer experience with Atoptech, Synopsys and Cadence: P&R, PT STA, Formal verification experience with SDC constraints debug complex high speed interfaces (serdes, DDR3, MIPI)
experience with IP integration
TCL and scripting
experience with advanced nodes (40nm and below)
BS of Electrical Engineering or similar. MSEE a plus.
Outstanding communications skills (including English) and team player
Thanks & Regards
Kavini Bitla
Agile Enterprise Solutions, Inc
Email : kavini_bitla@aesinc.us.com || www.aesinc.us.com
Agile Enterprise Solutions Inc || "Ensuring Client's Success"||
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