Hi Associates,
Hope you are doing well
Please take a look the Job description given and let me know if you are interested reply with your most updated resume.
Job Title: DFT Engineer
Location: Hillsboro - OR
Job Description:
· Use Spyglass DFT to ensure RTL or netlist can achieve world class ATPG coverage
o Run and debug DRC on Intel designs at 0.5, 0.8 and 1.0 milestone
o Develop scan_waivers.tcl and dfx_setup.tcl as handoff from RTL to Synthesis
o Raise bugs and follow through the bug closure process in HSD until it is disposition
· Use Synopsys DFTC to generate scan inserted netlist
o Run and debug DRC on Intel designs at 0.5, 0.8 and 1.0 milestone to generate scan inserted netlist
o Review DRC report to make sure all failures are clean and understood with INTEL engineers
o Update scan_waivers.tcl and dfx_setup.tcl if necessary
o Review of scan insertion and coverage point are world class with INTEL engineers
o Raise bugs and follow through the bug closure process in HSD until it is disposition.
· Use Mentor to ATPG and generate testbench
o Run and debug DRC on Intel designs at 0.5, 0.8 and 1.0 milestone
o Do low scan coverage debug and update scan_waivers.tcl and dfx_setup.tcl if necessary
o Raise bugs and follow through the bug closure process in HSD until it is disposition
o Generate testbenches for GLS
o Joint review with Intel engineers and updates to Intel
· Use VCS to GLS
o Run and debug GLS failure on Intel designs at 0.5, 0.8 and 1.0 milestone
o Raise bugs and follow through the bug closure process in HSD until it is disposition
o Develop and revision control GLS error free ATPG Ward and ASCII patterns as hand-off to post-silicon team
o Joint review of GLS results with INTEL engineers.
Thanks & Regards
Papireddy Beeram
Ph: 972-427-1720
Email: papireddy_beeram@aesinc.us.comYou received this message because you are subscribed to the Google Groups "IT JOBS in USA" group.
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