Job responsibilities:
B.E/M.E/M.Tech (Electronics & Communication/ VLSI)
VHDL RTL design targeting for the Actel FPGA devices
Board Level debugging (Experience with CROs & Logic Analyzers)
FPGA device synthesis flow for Actel FPGAs
Simulation using Modelsim Tool
Verilog design
Should be able to create Test cases for module wise in FPGA
Should be able to analyse and create BFM (Bus Function Model) and support in testing the hardware
Should be able to test the FPGA alone
Should be able to work with other colleagues like Firmware and Hardware team during integration testing
Should be able to stretch work hours on demand and some cases night shift also to be supported, no additional pay.
Should be able to work with Offshore team (India team)
Basic knowledge of understanding the hardware system and it’s interfaces on board level
Ability to analyse & synthesize design issues using VHDL RTL
Knowledge of SDRAM Controller / Manchester / ADC /DAC will be an added advantage
The resource should be able to join with in two weeks.
You received this message because you are subscribed to the Google Groups "IT JOBS in USA" group.
To unsubscribe from this group and stop receiving emails from it, send an email to it-jobs-in-usa+unsubscribe@googlegroups.com.
To post to this group, send email to it-jobs-in-usa@googlegroups.com.
Visit this group at http://groups.google.com/group/it-jobs-in-usa.
For more options, visit https://groups.google.com/groups/opt_out.
No comments:
Post a Comment